Semi F47 Background

The Computer Business and Equipment Manufacturers Association (CBEMA) curve was established in the late 1970s as a first attempt to determine the appropriate response of computer equipment to undervoltage conditions (sags and interruptions) and overvoltage conditions (swells).  In the 1990s EPRI benchmark studies in the nature of the electrical system determined that voltage sags were by far the most common in the power system.  In addition, EPRI research on computer power supplies in 1995 led to a revised CBEMA curve known as CBEMA 96 or the Information Technology Industry Council (ITIC) curve.  Existing electrical supply standards from IEC, CENELEC, IEEE, and SEMI were examined by the SEMI Power Quality and Equipment Ride-Through Task Force and documented in an internal task force report.  Furthermore, a database of over 1,000 voltage sag events was amassed from 15 different semiconductor sites.  This voltage sag magnitude-duration data was plotted and statistically analyzed to determine the common voltage sags that are experienced at semiconductor manufacturing facilities.  The scatter plot of the data is shown below with the CBEMA 96 (ITIC) curve overlaid on the graphic.

Pertinent equipment electrical tolerance standards must reflect an understanding of equipment design as well as an understanding of the electrical environments in which equipment is expected to operate.  The electrical disturbance data collected from the 15 different semiconductor sites provides a representation of the electrical environment for large semiconductor sites.  Because relevant information on the susceptibility for semiconductor manufacturing equipment did not exist at the onset of the standards process, testing was performed to determine actual tolerance to voltage sags.

An analysis of 30.5 monitor years of disturbance data collected at major semiconductor sites revealed that 166 or 15.4% of the events were below the CBEMA ‘96 tolerance curve.  Thirteen of the fifteen semiconductor sites averaged at least one event below the CBEMA curve each year.  Furthermore, the average number of occurrences below the CBEMA ‘96 curve per site, per year, was 5.4. Given this information, it was apparent to task force members that application of the CBEMA’96 curve would not yield satisfactory performance for semiconductor manufacturing equipment.  The task force concluded that a higher level standard was needed.

Semiconductor manufacturing equipment tests demonstrated that properly selected sub-components within the semiconductor equipment could consistently withstand voltage sags to 50% of nominal.  The number of sub-components that were capable of withstanding voltage sags more severe than 50% declined abruptly.  A 0.2-second duration for voltage sags of this magnitude was selected because of a requirement to have an even duration figure to accommodate 50-Hz rated equipment.  The figure was also selected for compatibility with fault clearing times for common protective devices present on the electrical systems.

Contour Plot with Semi F47 Tolerance Curve Overlaid

The contour plot represents the disturbance data collected at the 15 semiconductor sites.  The plot represents the number of occurrences that a given equipment tolerance curve will be exceeded during a one-year period.  Displayed on the plot is the tolerance curve that was proposed for semiconductor processing equipment.  The contour plot illustrates that the transitions in the proposed tolerance curve for semiconductor equipment tracks the contour line which represents the fewest number of expected events.